1. Field of Invention
The invention relates to a phase detecting circuit and a phase detecting method applied to a clock and data recovery circuit, and, in particular, to a phase detecting circuit, which has an adjustable gain curve and operates at a low frequency, and a method thereof.
2. Related Art
In the modern communication system, the way of high-speed sequential signal transmission has gradually replaced the previous parallel signal transmission. During the high-speed sequential signal transmission, the original low-speed parallel signal has to be converted into a high-speed sequential signal first to facilitate the transmission. Thus, a clock generating circuit for generating a high-speed clock signal for sampling the high-speed sequential signal is needed. At the receiving end, a clock and data recovery circuit for recovering the sampled high-speed sequential signal is needed. The clock and data recovery circuit typically has the architecture of a phase-locked loop circuit, which compares the sampled high-speed sequential signal (hereinafter referred to as the data signal) with a clock signal to generate a phase difference. Thus, the self-calibrations of the clock signal and the data signal can be achieved, and the error rate of recovering the data signal may be reduced.
Referring to FIG. 1, a conventional clock and data recovery circuit 1 includes a phase detecting circuit 11, a charge pump 12, a filter 13 and a voltage control oscillator 14. The voltage control oscillator 14 generates a clock signal CLK. The phase detecting circuit 11 detects a phase difference between a data signal DATA and the clock signal CLK to generate two control signals UP, DN. Herein, the control signals UP, DN control one set of switches 121 of the charge pump 12 to turn on one set of current sources 122 such that a current I inputted to or outputted from the set of current sources 122 charges/discharges the filter 13 to make the filter 13 generate an output voltage V. The voltage V can control the voltage control oscillator 14 to adjust the phase of the clock signal CLK such that the phase difference between the clock signal CLK and the data signal DATA may be kept constant.
The conventional phase detecting circuit 11 may be a linear phase detector or a bang-bang phase detector. However, when the phase detecting circuit 11 is the linear phase detector, the control signals UP, DN generated by the phase detecting circuit 11 operating at the ultra-high frequency cannot smoothly trigger the charge pump 12 to operate. So, the bang-bang phase detector is often used in the high-speed clock and data recovery circuit 1.
FIG. 2 is a circuit diagram showing the conventional bang-bang phase detector, which includes four D flip-flops 111-114 and two XOR gates 115, 116. The D flip-flop 111 is triggered at a rising edge of the clock signal CLK to sample the data signal DATA and output a signal Q1. The D flip-flop 113 is triggered at a falling edge of the clock signal CLK to sample the data signal DATA and output a signal Q3. Next, the D flip-flop 112 is triggered at the rising edge of the clock signal CLK to sample the signal Q1 and output a signal Q2. The D flip-flop 114 is triggered at the rising edge of the clock signal CLK to sample the signal Q3 and output a signal Q4. The XOR gate 115 processes the signals Q2, Q4 by the XOR operation to output a control signal UP. The XOR gate 116 processes the signals Q1, Q4 by the XOR operation to output a control signal DN. FIGS. 3 and 4 show signal timings when the bang-bang phase detector of FIG. 2 is operating. As shown in FIG. 3, when the control signal UP is enabled to be 1, the control signal UP controls the charge pump 12 to speed up the clock signal CLK generated by the voltage control oscillator 14. As shown in FIG. 4, when the control signal DN is enabled to be 1, the control signal DN controls the charge pump 12 to slow down the clock signal CLK generated by the voltage control oscillator 14.
FIG. 5 shows a gain curve of the above-mentioned phase detecting circuit 11. When the control signal UP is enabled to be 1, the charge pump 12 generates the current I according to the control signal UP. On the contrary, when the control signal DN is enabled to be 1, the charge pump 12 generates a current −I according to the control signal DN, and the curve is the fixed gain curve. Because the phase detecting circuit 11 utilizes the bang-bang phase detector, which is a nonlinear element, it is very difficult to analyze the gain curve in a linear way. Thus, when the clock and data recovery circuit 1 is applied to various systems, it is impossible to change the gain curve to increase the input jitter tolerance of the clock and data recovery circuit 1 with respect to the data signal DATA. The prior art adds extra circuits including a counter or an accumulator after the phase detecting circuit 11 in the clock and data recovery circuit 1 so as to compensate or correct the control signals UP, DN to increase the input jitter tolerance of the clock and data recovery circuit 1 with respect to the data signal DATA. However, these additional circuits also cause the signal delay between the phase detecting circuit 11 and the voltage control oscillator 14 and generate a larger jitter in the clock and data recovery circuit 1.
In addition, when the frequency of the data signal DATA is getting higher and higher, the phase detecting circuit 11 and the clock and data recovery circuit 1 also have to operate at the high-frequency to thus generate more noises, which deteriorate the circuit efficiency. In addition, the cost of the high-frequency circuit is higher, and the costs of the phase detecting circuit 11 and the clock and data recovery circuit 1 also cannot be reduced.